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TSMC Targets 2029 for Panel-Level CoPoS Packaging in AI Chip Push

TSMC is accelerating development of next-gen AI chip packaging technology CoPoS, moving from round 12-inch wafers to 310mm x 310mm square panels, with mass production not expected before 2029, according to DigiTimes.

June 30, 2026
2 min read
Source: Investing.com
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Key Numbers

mass production year
2029
panel size
310mm x 310mm

According to a report by DigiTimes, Taiwan Semiconductor Manufacturing (TSMC) is accelerating development of a next-generation AI chip packaging technology called CoPoS, which shifts production from round 12-inch wafers to 310mm x 310mm square panels. Mass production is not expected before 2029.

Details

TSMC has already launched a pilot line at VisEra's Longtan plant while imposing strict confidentiality agreements across its supplier base to guard proprietary know-how. The new technology aims to improve packaging efficiency and reduce costs, strengthening TSMC's ability to meet growing demand for AI chips.

Context

This move comes amid strong demand for advanced packaging solutions in the semiconductor industry, particularly from companies like NVIDIA (ticker: NVDA) that rely on TSMC's manufacturing for AI chips. Panel-level packaging is a significant advancement that could lower costs and increase throughput.

What This Means for Investors

While mass production is still years away, TSMC's investment in advanced packaging reinforces its leadership in the semiconductor market. NVIDIA (NVDA) investors may benefit from improved supply chain efficiency, but no immediate impact on stock prices is expected.

Frequently Asked Questions

CoPoS is a next-generation AI chip packaging technology that uses 310mm x 310mm square panels instead of round 12-inch wafers, aiming to improve efficiency and reduce costs.

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This article was rewritten in Wrqti's editorial style based on information from the original source above. Content is informational only — not investment advice.